1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a sense amplifier control signal generating circuit for controlling the data retention mode (DR mode).
2. Background Art
In semiconductor memory devices such as dynamic and pseudo-static RAM, a memory cell usually comprises a storage capacitor and an access transistor. Data stored in the storage capacitor suffers a loss of charge after a certain period of time, and therefore requires to be periodically refreshed. The refresh mode periodically refreshes the storage capacitor using a signal external to the semiconductor device. The data retention mode is periodically refreshed by the automatic operation of a timer and refresh-related circuit only if a condition specified for the data retention mode is met. The data retention mode does not require an external signal to periodically control the storing of the data using a low operational voltage (battery voltage) and the device used for the retention mode is necessarily provided in a recently developed semiconductor.
The fundamental cell array and the structure of a sense amplifier of a dynamic RAM are illustrated in FIG. 1. A memory cell array comprising a storage capacitor Cs for storing data and an access transistor M for transferring the stored data to bit lines are shown. N-type and P-type sense amplifiers are connected to a pair of adjacent bit lines BL and BLB. The gate of the access transistor M is connected to the word line signal .phi.WL produced by a row decoder. An N-type drive transistor Mn is connected to the common node of sensing transistors 3 and 4 of the N-type sense amplifier in order to drive it by receiving a signal .phi.N. A P-type drive transistor Mp is connected to the common node of sensing transistors 1 and 2 of the P-type sense amplifier in order to drive it by receiving a signal .phi.P.
A conventional sense amplifier control signal generation circuit is shown in FIG. 2 for controlling the sense amplifiers. The operational voltage waveforms of the circuit shown in FIG. 1 are illustrated in FIG. 3 according to the outputs of FIG. 2. The circuit of FIG. 2 comprises a first delay circuit 10 for delaying and amplifying the word line signal .phi.WL to generate the signal .phi.N, and a second delay circuit 20 for inverting and delaying the output of the first delay circuit 10. The delay circuits 10 and 20 may comprise a CMOS inverter, resistor and capacitor.
The operational characteristics of the circuit of FIG. 1 are described with reference to FIG. 3 including the circuit of FIG. 2. The delay path (namely, first and second delay circuits 10 and 20) is used in both the normal and data retention modes, so that the N-type and P-type sense amplifiers have the same sensing time in the normal and retention modes. In this case, after the word line has been enabled, the signal .phi.N becomes high thereby turning on N-type drive transistor Mn to drive the N-type sense amplifiers 3 and 4. Also, after a delay time at the second delay circuit 20, the signal .phi.P becomes low turning on the P-type transistor Mp to drive P-type sense amplifiers 1 and 2. The first and second delay circuits 10 and 20 respectively control the time interval t1 between the enabling of the word line and the starting of the N-type sense amplifiers 3 and 4, and the time interval t2 between the starting of the N-type sense amplifiers and the starting of the P-type sense amplifiers 1 and 2. The time interval t1 is taken for charge sharing during which the charge of the storage capacitor Cs is sufficiently transferred to the bit lines. However, it is preferable to keep the time intervals t1 and t2 as short as possible in order to increase the operational speed.
A conventional circuit such as the one shown in FIGS. 1 and 2 causes a problem in the data retention mode. If the time interval t1 is reduced in order to increase the operational speed, the charge sharing time becomes insufficient, causing a failure of the memory cell operation. Also, if the time interval t2 is reduced, a direct current flows from the voltage source terminal Vcc of the N-type sense amplifiers to the ground voltage terminal Vss of the P-type sense amplifiers. The amount of the direct current increases as the time interval t2 is reduced.